1. Field of the Invention
The present invention relates to the field of semiconductor processing and more particularly to a method of fabricating ultra thin gate dielectrics using a chemical mechanical polishing technique.
2. Description of the Relevant Art
The fabrication of MOS (metal-oxide-semiconductor) transistors within a semiconductor substrate is well known. Typically, the substrate is divided into a plurality of active and isolation regions through an isolation process such as field oxidation or shallow trench isolation. A thin oxide is then grown on an upper surface of the semiconductor substrate in the active regions. This thin oxide serves as the gate oxide for subsequently formed transistors. Next, a plurality of polysilicon gate structures are formed wherein each polysilicon gate traverses an active region effectively dividing the active region into two regions referred to as the source region and the drain region. After formation of the polysilicon gates, an implant is performed to introduce an impurity distribution into the source/drain regions.
As transistor channels shrink below 0.5 micron, the limitations of conventional transistor processing become more apparent. To combat short channel effects in these smaller transistors, the depth of the source/drain junctions and the thickness of the gate oxides must be reduced. Thin oxides present significant manufacturing challenges to the manufacturer. The uniformity of the gate dielectric film across the wafer becomes more critical as the film thickness decreases. A 5 angstrom variation in film thickness across a wafer is far more significant in a 50 angstrom film than a 150 angstrom film. Greater control over oxide growth rates, uniformity, and etch rates is needed to insure that the thinner dielectric can be consistently reproduced in a manufacturing environment. Conventional gate formation techniques, which typically consist of immersing a plurality of wafers into an oxidation tube maintained at a temperature sufficient to thermally oxidize exposed silicon, do not provide sufficient film thickness control for the reliable fabrication of ultra-thin films (i.e., films with a thickness less than approximately 65 angstroms).
Despite the manufacturing difficulties noted, thin gate dielectrics are desirable not only to minimize short channel effects, but also because the transistor drive current is roughly inversely proportional to the gate oxide thickness over a wide range of operating conditions. Because higher drive currents result in faster devices, a great deal of effort has been directed towards reducing the gate oxide thickness (as well as other transistor geometries including channel length and junction depth) without significantly reducing the reliability of the integrated circuit. Therefore, it would be highly desirable to fabricate ultra-thin MOS gate dielectrics with a consistently reproducible and manufacturable process.